Patent · US Active

Current mode logic latch

US8736334B2 · kind B2 · utility

3Cited by

2References

11Claims

0Family size

Assignee

FUJITSU LIMITED · JP

Inventors

Shuo-Chun Kao · Sunnyvale, US
Nikola Nedovic · San Jose, US

Key dates

Filing date	Jun 13, 2012
Grant date	May 27, 2014
Priority date	—
Expiry date	Jul 18, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/356043
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.