Successive approximation analog-to-digital conversion architectural arrangement for receivers
US8736480B1 · kind B1 · utility
14Cited by
6References
24Claims
0Family size
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Key dates
| Filing date | Jan 11, 2013 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Jan 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method of successive approximation analog-to-digital conversion for receivers comprising that during a sample mode, connecting an array of capacitors to a plurality of sampling switches coupled to a plurality of amplified input signals, and during a conversion mode, connecting in common the array of capacitors to a comparator and isolating the array of capacitors from the plurality of sampling switches. Additionally, filtering is done by the summation of samples at phase offsets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.