Multi-core processor architecture for active autostereoscopic emissive displays
US8736675B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2007 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Apr 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03H2226/02
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In one implementation, a system includes a multi-core processor and an optical display with a plurality of hogels. Each hogel is configured to radiate light in a plurality of directions, with controllable intensities in each of the plurality of directions. The multi-core processor is coupled to the optical display and configured to control the hogels. The multi-core processor includes at least two cores, an on-chip memory, and a master processor in a single integrated circuit package. The master processor may be a general-purpose on-chip processor, such as a core in the multi-core processor, that is used to coordinated operations of the other cores. Each of the cores is configured to receive hogel data and to generate signals for a corresponding subset of the plurality of hogels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.