Shared memory multi video channel display apparatus and methods
US8736757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Jun 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/42638
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.