System and method to read a memory cell with a complementary metal-oxide-semiconductor (CMOS) read transistor
US8737117B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 2010 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Apr 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to manage leakage of a complementary metal-oxide-semiconductor (CMOS) read transistor in a memory cell. In a particular embodiment, a memory cell is disclosed that includes a storage element and a complementary metal-oxide-semiconductor (CMOS) read transistor. The CMOS read transistor includes a first terminal coupled to a read word line, a second terminal coupled to a read bit line, and a third terminal coupled to the storage element. During a non-read operating time, the read word line and the read bit line are both maintained at substantially the same voltage level. During a read operation, the read word line is maintained at a particular voltage level until after a voltage representing data stored at the storage element is sensed by the CMOS read transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.