Configuring routing in mesh networks
US8737392B1 · kind B1 · utility
6Cited by
23References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2011 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Mar 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/126
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions in which an ordering of dimensions for routing data is configurable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.