Analog-to-digital converter based decision feedback equalization
US8737491B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2010 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Aug 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for Analog-to-Digital Converter Based Decision Feedback Equalization. The method may include providing an integrated circuit including a SERDES circuitry having a transmit circuitry and a receiver circuitry and receiving a high-speed data stream at the receiver circuitry. The method may also include converting the high-speed data stream to a digital signal using a successive approximation analog-to-digital converter and providing the digital signal to a digital decision feedback equalization circuitry via the successive approximation analog-to-digital converter. The method may also include generating an output signal at a phase locked loop and receiving the output signal at a multi-loop clock and data recovery circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.