Gate-level logic simulator using multiple processor architectures
US8738349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2010 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Nov 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and optimizing the descriptions of the integrated circuit design for efficient simulation on a parallel processor, more particularly a SIMD processor. The description may be segmented into cluster groups, for example macro-gates, formed of logic elements, where the cluster groups are sized for parallel simulation on the parallel processor. Simulation may occur in an oblivious as well as event-driven manner, depending on the implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.