Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions
US8738891B1 · kind B1 · utility
16Cited by
151References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2005 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Jun 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/86
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing command acceleration. The method includes receiving a first set of instructions from a first processor, wherein the first set of instructions are formatted in accordance with a microarchitecture of the first processor. The first set of instructions are translated into a second set of instructions, wherein the second set of instructions are formatted in accordance with a microarchitecture of a second processor. The second set instructions are then transmitted to the second processor for execution by the second processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.