Memory error detecting apparatus and method
US8738976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2011 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Dec 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.