Memory subsystem having a first portion to store data with error correction code information and a second portion to store data without error correction code information
US8738995B2 · kind B2 · utility
2Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2009 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Mar 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprising a memory subsystem having at least one memory device, and a memory controller to control access of the memory subsystem, wherein the memory controller is configured to store data with error correction code (ECC) information in a first portion of the memory subsystem, and to store data without ECC information in a second portion of the memory subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.