Techniques for segmenting of hardware trace and verification of individual trace segments
US8739091B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Nov 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic verification program, method and system that segments simulation results and then processes the resulting segments separately, and optionally in parallel, reduces memory and other system requirements and improves efficiency of verification of digital logic designs. The verification process fixes up event dependency check for past-directed checkers by including additional information with each segment after an initial segment that describes at least a portion of a state of the logic design, so that resultant events in the current segment that are caused by events in the previous segment(s) can be traced back to those events. Future directed checks are fixed-up by either repeating a failed check with a concatenation of the current segment and a next segment, or by providing an overlap between segments to ensure that the expected time duration between a causative event and the resulting event are included within the same segment file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.