Systems and methods for reducing logic switching noise in parallel pipelined hardware
US8739101B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Nov 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.