Techniques for placement in highly constrained architectures
US8739103B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2013 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Oct 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for placement in highly constraint chip architectures are described herein. In an example embodiment, a computer system places a digital portion of an electronic design for a programmable chip. The programmable chip comprises multiple fixed-function blocks and a plurality of pins, where each one of the multiple fixed-function blocks can be coupled only to a respective subset of the plurality of pins. The electronic design comprises a particular fixed-function block (FFB) instance that is connected to a particular input-output (IO) instance. The computer system places (e.g., by using a backtracking search) the particular FFB instance on a particular fixed-function block and the particular IO instance on a particular pin from a particular subset of the plurality of pins, where in the programmable chip the particular fixed-function block can be coupled only to the particular subset of the plurality of pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.