Transistors with isolation regions
US8742460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2010 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Jan 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.