Method for making via interconnection

US8742588B2 · kind B2 · utility

Assignee

• ÅAC Microtec AB · SE

Inventors

• Peter Nilsson · Solna, SE
• Jürgen Leib · Freising, DE
• Robert Thorslund · Sigtuna, SE

Key dates

• Filing date: Oct 15, 2009
• Grant date: Jun 3, 2014
• Expiry date: Oct 15, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/1461
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention provides a method of forming a via hole (9), or a via (7), from a lower side (5) of a substrate (3) for electronic devices towards an upper side (4) of a substrate (3) at least partly through the substrate (3). The method comprises the steps of: etching a first lengthwise portion (11) of the via hole (9) and etching a second lengthwise portion (12) of the via hole (9); whereby the first lengthwise portion (11) and the second lengthwise portion (12) substantially form the via hole (9) and a constriction (23) is formed in the via hole (9). The constriction (23) defines an aperture (24) of the via hole (9) and the method further comprises the step of opening the via hole (9) by etching, with the constriction (23) functioning as an etch mask. A via is formed by at least partly filling the via hole with conductive material. A substrate for electronic devices comprising a via is also provided.