Interconnected array of logic cells reconfigurable with intersecting interconnection topology
US8742789B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 14, 2010 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Dec 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interconnected array of reconfigurable logic cells which carry out at least one logic function, externally connected to peripheral connection network equipped with switch boxes and connected to programmable input/output blocks. The logic cells are distributed in a first dimension in rows i with i=1 to d and a second dimension in columns j with j=1 to w, with d≦2 and w=2 or d=2 and w≦2, each logic cell including a second input, a second input, a first output and a second output, the first input of each logic cell and the first output of each logic cell being connected to the connection network, the second input and the second output of each logic cell being connected to other different column and row logic cells except for the first and last rows or columns for d>2 or w>2 respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.