Level shifter
US8742821B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 2011 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Aug 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a level shifter. In an embodiment, the level shifter includes first to sixth transistors. The first and second transistors have common control nodes coupled to a first bias voltage, receive a pair of input signals and respectively provide a first output node and a second output node. The fifth and sixth transistors have common control nodes coupled to a second bias voltage to form a current mirror. The third transistor is coupled between the first and the fifth transistors and has a control node coupled to the second output node. The fourth transistor is couple between the second and the sixth transistors and has a control node coupled to the first output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.