PWM re-clocking scheme to reject accumulated asynchronous jitter
US8742841B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2012 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Dec 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/03
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier may use pulse-width modulators controlling respective sets of switches to produce an amplified version of a source signal. A phase locked loop in the amplifier may generate a differential clock signal. A first processing element operating according to a first supply voltage may generate a PWM signal representative of the source signal, and also generate a clock enable signal corresponding to the differential clock signal. A second processing element (PE2) may receive the differential clock signal, the PWM signal, and the clock enable signal, and level shift the PWM signal and the clock enable signal to operate according to a second supply voltage, and may generate a resampling clock signal from the differential clock signal according to the level shifted clock enable signal. The PE2 may provide a PWM output signal representative of the source signal by resampling the level shifted PWM signal with the resampling clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.