High efficiency power amplifier architecture for off-peak traffic hours
US8742842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2012 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Aug 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7239
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplifier architecture includes high and low power paths. The high power path may include a number of different amplifier structures. The low power path includes a switching element configured to short a signal line to ground or provide an open between the signal line and ground. The low power path and an output of the high power path are summed at a summing junction. Circuitry, responsive to one or more control signals, is configured in a high power mode to turn on amplifier(s) in the amplifier structure, route an input signal through a driver amplifier to the high power path and place the switching element in one of the open/closed positions; the circuitry is configured in a low power mode to turn off the amplifier(s), route the input signal through a driver amplifier to the low power path and place the switching element in the other position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.