Patent · US Active

Avionics display architecture with independent processing and monitoring channels

US8743020B1 · kind B1 · utility

8Cited by
2References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 26, 2012
Grant dateJun 3, 2014
Priority date
Expiry dateDec 12, 2032

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG09G2380/12
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A high integrity, high availability avionics display architecture for an avionics display system. The architecture includes a plurality of display processing computers (DPC) and a plurality of display integrity feedback interfaces. Each DPC includes at least two independent processing channels. Each independent processing channel includes at least two independent lanes. Each independent lane includes an I/O section and a processor section. Furthermore, each independent processing channel comprises an operative graphics section. At least one of the independent lanes provides a critical display function that provides commands to the graphics section to drive a display signal to displays of the avionics system. A number of display integrity feedback interfaces from the displays of the avionics display system provide integrity by allowing the integrity monitor functions to detect faults within the display signals and/or originating from the displays.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.