Fixed-point processing using quantization levels based on floating-point processing
US8743493B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2013 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Jan 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/10268
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry comprises a detector and a decoder coupled to the detector. The detector is configured to perform fixed-point detection on a digital data signal using a first set of quantization levels determined based at least in part on a result of a floating-point detection of the digital data signal. The decoder is configured to perform fixed-point decoding on an output of the detector using a second set of quantization levels determined based at least in part on a result of a floating-point decoding of the output of the detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.