On-chip eye viewer architecture for highspeed transceivers
US8744012B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2012 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Jun 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31711
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
System, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with a serial input signal either during or after equalization. The device may include an equalizer and eye viewer circuitry configured to select a node of the equalizer for eye monitoring of the input signal, which may be during or after equalization. In one embodiment, the eye viewer circuitry may provide a separate sampler for each respective node, while sharing a control logic and phase interpolator among the samplers. The eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the serial input signal, as seen from the selected node of the equalizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.