Network delay analysis including parallel delay effects
US8745215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2011 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Dec 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/28
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The embodiments facilitate the analysis of application delays, including delays that occur on multiple paths. A trace file of an application's network events is processed to categorize the causes of delays incurred in the propagation and processing of these events. The system identifies the amount of delay that can be eliminated by eliminating each of the components of delay individually, as well as the amount of delay that can be eliminated by eliminating combinations of the delay components. A user interface displays the amount of reduction that can be achieved by eliminating various delays alone or in combination. The interface also allows the user to view the individual delay components contained in combinations of delay components. In this manner, the user is provided a view of each of the delay components that would need to be addressed, either individually or in combination, to improve the overall application delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.