Remapping for memory wear leveling
US8745357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2009 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Nov 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a corresponding apparatus provide for remapping for wear leveling of a memory. The method is implemented as logic and includes the steps of receiving a memory operation, the memory operation including a logical memory address; dividing the logical address into a logical block address portion, a logical line address portion, and a logical subline address portion; translating the logical block address portion into a physical block address; selecting a line remap key; applying the line remap key to the logical line address portion to produce a physical line address; producing a physical subline address portion; and combining the physical block, line, and subline address portions to produce a physical address for the memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.