Processor to execute shift right merge instructions
US8745358B2 · kind B2 · utility
11Cited by
63References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2012 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Sep 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.