Providing an on-die logic analyzer (ODLA) having reduced communications
US8745455B2 · kind B2 · utility
4Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2010 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Sep 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/25
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.