Memory with segmented error correction codes
US8745472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2012 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Feb 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2942
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A code word is received that was derived from a plurality of smaller code words that represent a data word of 2m data bits and a plurality of error correction code bits. The code word is converted into the plurality of smaller code words and syndromes are computed by multiplying each of the plurality of smaller code words by a check matrix. The syndrome words are processed to determine a number of errors that exist in each of the plurality of smaller code words. A portion of the syndrome words is processed to determine locations of possible errors within the plurality of smaller code words. Up to two errors may be corrected and up to three errors may be detected in the code word by using the number of errors and the locations of possible errors to determine erroneous bits in the code word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.