Connection to first metal layer in thin film transistor process
US8748320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2012 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Sep 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
A method of connecting to a first metal layer in a semiconductor flow process. Disclosed embodiments connect to the first metal layer by etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer, depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole, and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.