Super junction transistor and fabrication method thereof
US8748973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2012 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Dec 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.