Calibration of interleaving errors in a multi-lane analog-to-digital converter
US8749410B1 · kind B1 · utility
11Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Dec 19, 2012 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Dec 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.