Display device for reducing parasitic capacitance with a dummy scan line
US8749469B2 · kind B2 · utility
1Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2008 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Mar 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display device, in at least one embodiment, includes: a gate driver including a plurality of shift register stages each provided so as to correspond to each row, the gate driver outputting a gate signal for turning on switching elements in the each row; and a source driver outputting a data signal in accordance with an image to be displayed. For a row (first row) located at an outermost position from which scanning by use of the gate signal starts, a dummy line is provided. The dummy line is driven by a gate start pulse inputted into a shift register in the first row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.