Method and system for coordinated data execution using a primary graphics processor and a secondary graphics processor
US8749561B1 · kind B1 · utility
5Cited by
62References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2003 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Mar 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/363
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.