Semiconductor storage device
US8750052B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2012 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Dec 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a sense amplifier connected to one or more of bit lines and configured to sense data stored in the memory cells; and a word line driver configured to control a voltage of one or more of word lines. The memory cells constitute a memory block. The memory cells constitute a memory block being a unit of memory cells on which a data erasing operation is performed. A controller changes an erase condition during the data erasing operation performed on the memory block or a verify condition for a verify check of verifying whether the data has been erased from the memory cells in the memory block, in proportion to a ratio of number of predetermined logical value data to the data in the memory block or the page before the data erasing operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.