Memory system, memory test system and method of testing memory system and memory test system
US8750061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.