Single wire bus interface
US8750324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2009 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Apr 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/403
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.