Method and apparatus for using a shared ring buffer to provide thread synchronization in a multi-core processor system
US8751737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Aug 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for improving synchronization between threads in a multi-core processor system are provided. An apparatus includes a memory, a first processor core, and a second processor core. The memory includes a shared ring buffer for storing data units, and stores a plurality of shared variables associated with accessing the shared ring buffer. The first processor core runs a first thread and has a first cache associated therewith. The first cache stores a first set of local variables associated with the first processor core. The first thread controls insertion of data items into the shared ring buffer using at least one of the shared variables and the first set of local variables. The second processor core runs a second thread and has a second cache associated therewith. The second cache stores a second set of local variables associated with the second processor core. The second thread controls extraction of data items from the shared ring buffer using at least one of the shared variables and the second set of local variables.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.