Method for design partitioning at the behavioral circuit design level
US8751983B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2013 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Mar 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design partitioning method and apparatus includes an RTL reader module configured to receive, process, and parse hardware descriptive language of a circuit design; an expression graph module configured to trace identified signal dependencies to determine dependent elements along selected paths within the circuit design; a hierarchy flattener module configured to remove existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements; a partition specification reader module that defines selected paths within the circuit design into a partition specification; a design partitioner module configured to separate the flattened circuit design hierarchy according to the partition specification; a re-partitioner module configured to create a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the circuit design; and an RTL design write-out module configured to output the second hierarchical circuit design structure for analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.