Method of common-centroid IC layout generation
US8751995B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2013 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Jun 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of common-centroid IC layout generation includes the following steps of acquiring a netlist of one circuit-element set; summing up the numbers of the unit element of all elements of the circuit-element set to get the total number of the unit elements and then determine the unit element array, the aspect ratio of which is closest to 1, via a combination operation; generating multiple common-centroid placements according to the unit element array and applying global routing assignment to each of the common-centroid placements; proceeding with cost evaluation in such a way that a cost calculation is applied to each of the common-centroid placements to get a corresponsive value; and comparing all of the common-centroid placements according to the values got from the cost evaluation and selecting the common-centroid placement corresponding to one of the values according to a predetermined condition for detailed routing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.