Patent · US Active

Fractional divider for avoidance of LC-VCO interference and jitter

US8754682B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

STMICROELECTRONICS (CANADA), INC. · CA

Inventors

John Hogeboom · Ottawa, CA
Anton Pelteshki · Carleton Place, CA

Key dates

Filing date	Apr 18, 2012
Grant date	Jun 17, 2014
Priority date	—
Expiry date	Apr 18, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/24
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.