Delay locked loop
US8754685B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Nov 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0805
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a delay line and a delay locked loop. The circuit is configured to receive a delay parameter and a clock signal. The delay locked loop is configured to generate a pair of control codes based on a frequency of the clock signal and a frequency of an oscillator of the delay locked loop. The delay locked loop is configured to determine a difference between the frequency of the clock signal and the frequency of the oscillator based on a phase of an output of the oscillator and a phase of the clock signal after the output of the oscillator and the clock signal are aligned. The delay line is configured to receive an input signal and generate an output signal delayed from the input signal by a time delay that corresponds to a delay line control code calculated from the pair of control codes and the delay parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.