PLL circuit with improved phase difference detection
US8754713B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 23, 2010 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Dec 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/193
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.