Methods and apparatus for calibrating pipeline analog-to-digital converters
US8754794B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Jul 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit with a pipeline analog-to-digital (A/D) converter and associated calibration circuitry is provided. The A/D converter may include multiple series-connected pipeline stages at least some of which are implemented using a switched capacitor configuration. The calibration circuitry may include an analog error correction circuit, a digital error correction circuit, and a calibration control circuit for coordinating the operation of the analog and digital error correction circuits. During calibration operations, the analog error correction circuit may be used to suitably adjust a gain setting for each pipeline stage, whereas the digital error correction circuit may be used to compute a code offset value for each pipeline stage. Calibration may proceed from a least-significant-bit pipeline stage towards a most-significant-bit pipeline stage, one stage at a time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.