Partition-free multi-socket memory system architecture
US8754899B2 · kind B2 · utility
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15References
20Claims
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Key dates
| Filing date | Mar 5, 2013 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Mar 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.