Flexible and efficient memory utilization for high bandwidth receivers, integrated circuits, systems, methods and processes of manufacture
US8755675B2 · kind B2 · utility
5Cited by
15References
43Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2007 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Dec 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic circuit (300) includes a signal processing circuit (310) including first and second signal processing blocks (310.1, 310.3) coupled in cascade, a memory circuit (320) coupled to and adjustable between the first and second signal processing blocks (310.1, 310.3), the memory circuit (320) having memory spaces, the memory circuit (320) configurable to establish a trade-off of the memory spaces between the first and second signal processing blocks (310.1, 310.3), and a configuring circuit (330) operable to configure the trade-off of the memory spaces of the memory circuit (320).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.