Multirank DDR memory modual with load reduction
US8756364B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2011 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Oct 27, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated at least in part to a first number of chip-select signals. The circuit is configurable to receive address signals and a second number of chip-select signals from the computer system. The circuit is further configurable to generate and transmit phase-locked clock signals to the first number of ranks, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.