Apparatus and method for enhancing flash endurance by encoding data
US8756365B2 · kind B2 · utility
16Cited by
2References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2010 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Nov 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Input bits are stored in memory cells by mapping the input bits into a larger number of transformed bits using a shaping encoding that has a downward asymptotic bias with respect to a mapping of bit patterns to cell states and programming some of the cells according to that mapping of bit patterns to cell states. The programmed cells are erased before being programmed to store any other bits. The invention sacrifices memory capacity to increase endurance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.