Controlling DRAM at time DRAM ready to receive command when exiting power down
US8756395B2 · kind B2 · utility
10Cited by
107References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Feb 27, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.