Method for forming bumps in substrates with through vias
US8759215B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 6, 2009 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Aug 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.