Array substrate and method of fabricating the same
US8759823B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Dec 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/00
Abstract
A fabricating method of an array substrate includes forming source and drain electrodes in each of pixel regions on a substrate; forming an organic semiconductor layer and a gate insulating layer on the source and drain electrodes, the organic semiconductor layer having an island shape and contacting facing ends of the source and drain electrodes, the gate insulating layer having a same plane shape as the organic semiconductor layer; forming a first passivation layer on the gate insulating layer; forming a gate electrode on the first passivation layer in the pixel region, the gate electrode corresponding to the gate insulating layer; forming a second passivation layer on the gate electrode, the second passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer, the pixel electrode contacting the drain electrode through the drain contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.